The fabrication of semiconductor devices according to various bulk and SOI protocols is known. In the former, neighboring devices are mutually isolated by intervening deep trenches that are filled with an insulative or dielectric material. Typically, if the bulk material is silicon, the trenches are filled with silicon oxide. In following SOI protocols, a thin layer of a semiconductor is formed on an insulative material. Thereafter, shallow trenches are formed through the semiconductor layer, typically silicon, and are filled with an insulative material, typically silicon oxide.
The major advantage of a bulk substrate over an SOI substrate is that the bulk substrate is substantially less expensive. However, certain devices, such as field effect transistors (FETs), fabricated on and in SOI substrates have several operational advantages over devices fabricated on and in bulk substrates.
It is known that the source/drain-to-substrate junction capacitance of an FET fabricated according to SOI protocols is lower than the source/drain-to-substrate junction capacitance of an FET formed in a bulk-silicon substrate. Further, SOI techniques allow drain current to be significantly higher at low voltages. Thus, as compared to bulk-silicon FETs, FETs fabricated pursuant to SOI protocols exhibit higher speeds (about 20%-35% or more), if both are operated at the same voltage, and reduced power consumption (about 35%-70% or more), if both are operated to give the same speed performance.
Moreover, latchup is eliminated in SOI FETs, which, in conjunction with the ability to retain low intra-well and inter-well leakage currents due to dielectric isolation, permits reduction in isolation spacing design rules, thus permitting increased packing density. Additional advantages of SOI devices with respect to bulk devices include: reduced soft error sensitivity, improved turn-on characteristic, reduced leakage current, and improved reliability by eliminating junction spiking.
There has recently emerged a so-called silicon-on-nothing (“SON”) technology, sometimes referred to as empty-space-in-silicon (“ESS”). See, for example, U.S. Pat. Nos. 6,630,714 to Sato et al. (“'714 patent”) and 6,579,738 to Farrar, et al. (“'738 patent”), and U.S. Published application 20030173617 to Sato, et al. (“'617 published application”); “Toshiba Finds ‘Nothing’ Makes a Better Transistor,” by Goodwins, 12/5/01, at http://news.zdnet.co.uk/hardware/chips/0.39020354,2100428.00.html (“Goodwins”); Oyo Buturi [a monthly publication of the Japan Society of Applied Physics], Vol. 69, No. 10, pp. 1187-1191, circa 2000, “Formation of SON (Silicon on Nothing) Structure Using Surface Migration of Silicon Atoms,” by Sato et al. at http://www.jsap.or.ip/ap/2000/ob6910/p691187.html (“Sato”); “Silicon Process Produces Pockets,” by Patch, in Technology Research News, Dec. 20/27, 2000, at http://www.tnrnag.com/122000/silicon_process_produces_pockets—122000.html (“Patch”); and “Empty-Space-In-Silicon Technique for Fabricating a Silicon-On-Nothing Structure,” by Mizushima, et al., in Applied Physics Letters, Vol. 77, No. 20, Nov. 13, 2000, pp. 3290-3292 (“Mizushima”).
The '714 patent discloses an FET formed on a thin silicon layer closing the open top of a cavity formed in a silicon substrate, the sides of the source and drain of the FET abutting STI. Neither the method of forming the cavity nor the method of closing the cavity with the thin semiconductor layer are disclosed.
The '738 patent discloses a method of forming a closed, isolated cavity within a silicon body. A cylindrical hole is formed in the substrate. Thereafter, the substrate is annealed in a deoxidizing ambient, such as hydrogen gas (pressure about 10 torr) at a high temperature (about 1100° C.) to effect self-organized migration of silicon atoms on the surfaces (wall and bottom) of the hole (a description of which effect is attributed to Sato et al., in “Substrate Engineering for the Formation of Empty Space in Silicon Induced by Silicon Surface Migration,” in 1999 IEDM Digest, paper 20.6.1). During annealing the silicon atoms migrate so that their surface energy is minimized. After about one minute, the shape and morphology of the hole changes drastically to that of a sphere-shaped void within the substrate. The hole first closes, then vanishes. A line or matrix of such holes may be similarly treated to form, respectively, a pipe-like void or a plate-like void within the substrate. One or more interconnect holes are then formed in the substrate to intersect the buried void. The interconnect hole and the void are then filled with a selected conductive material.
The '617 published application discloses a method of forming an isolated, closed void in a silicon substrate to achieve benefits like those achieved by SOI. The void ultimately resides beneath the channel of an MOS transistor. The method involves forming a groove having an aspect ratio greater than a critical value in the surface of the substrate and then subjecting the substrate to annealing like that of the '738 patent, except that the annealing time is said to be 10 minutes. This annealing “clos[es] the open portion of the groove . . . to thereby form a cavity.” Indeed, according to the '617 published application, “The important thing with the cavity . . . is that the open portion of the groove with a high aspect ratio is closed by performing a high-temperature annealing to change the groove into a cavity.”
Mizushima, apparently describing the work leading to the '617 application, is to the same effect as the '617 application. Annealing, as in the '617 application, is performed to close a trench or hole formed in a silicon substrate to form a closed void or cavity within the substrate. Mizushima notes that, “[I]n the case of . . . trenches . . . each trench broke up to a spherical empty space or spaces.”
Referring to FIG. 1, the '738 patent, the '617 published application, and Mizushima illustrate that, as a silicon substrate 10 having a hole 12 formed therein, FIG. 1(A), is subjected to annealing, the lower portion of the hole 12 first begins to round and the upper wall portions of the hole or trench begin to close, FIGS. 1(B)-1(D). Further rounding of the lower portion and closing of the upper wall portion of the hole 12 continue as annealing continues, FIG. 1(E). Then, a spheroidal void 14 begins to form, FIGS. 1(D) through 1(F), as the superjacent portion of the hole 12 continues to shrink, FIG. 1(D), closes or pinches off, FIG. 1(E), and becomes discontinuous from the void 14, FIG. 1(F). The hole 12 continues to shrink and closes above the void 14, FIG. 1(G). Finally, the hole 12 disappears, leaving only the void, FIG. 1(H). If a line of holes 12 are formed sufficiently close together, their voids 14 merge to form a pipe-like void (not shown). If a matrix of holes 12 is formed sufficiently close together, their voids 14 merge to form a plate-like void (not shown).